Field
Various features relate to a semiconductor device comprising a mold for top side and sidewall protection.
Background
A typical die is manufactured by depositing several metal layers and several dielectric layers on top of a substrate. The die is manufactured by using a wafer level packaging (WLP) process. The substrate, metal layers and dielectric layers are what form the circuit elements of the die. Multiple dies are usually manufactured on a wafer. FIG. 1 illustrates a plan view of a wafer 100 that includes several uncut dies 102. Each uncut die includes a substrate, metal layers and dielectric layers. The wafer 100 is then cut into individual/single dies. FIG. 1 also illustrates vertical and horizontal scribe lines 102-104. Scribe lines are portions of the wafer 100 that are cut in order to manufacture the individual dies (e.g., die 102).
FIG. 2 illustrates a side view of a wafer. Specifically, FIG. 2 illustrates a side view of a portion of a wafer 200. The wafer 200 includes several metal and dielectric layers 202, a pad 204, a passivation layer 206, a first insulation layer 208, a first metal layer 210, a second insulation layer 212, and an under bump metallization (UBM) layer 214. FIG. 2 also illustrates a solder ball 216 on the wafer 200. Specifically, the solder ball 216 is coupled to the UBM layer 214. The pad 204, the first metal layer 210 and the UBM layer 214 are a conductive material (e.g., copper). The first insulation layer 208 and the second insulation layer 212 are polyimide layers (PI), Polybenzoxazole (PBO) or other polymer layers used for repassivation. FIG. 2 also illustrates a region of the wafer 200 that will be cut to create individual dies. This region of the wafer 200 is illustrated by the scribe line 218, which may correspond to either of the scribe lines 104-106 of FIG. 1.
During the process of cutting the wafer (e.g., wafers 100, 200) into one or more dies, a lot of stress (e.g., thermal stress, mechanical stress) is applied to the die. The resulting stress on the die may affects components of the die and/or the package, including the metal layers, the dielectric layers, the passivation layer, the UBM layer, and/or the solder balls. The metal layers, the dielectric layers and the passivation layer of the die are especially susceptible to stress. In particular, low K (LK) dielectrics or extremely low K (ELK), or ultra low K (ULK) dielectrics tend to be brittle and can easily crack/chip under stress. This stress can result in the chipping and/or cracking of the die, which ultimately results in a defective die.
Therefore, there is a need for a design to stop and/or prevent the propagation of a crack and/or chipping of a die.